To solve the problems associated with low memory accessing speed, a multi-level cache architecture is introduced according to temporal and spatial locality features of data. The term cache refers to one or more small-size high-speed associated storage devices. When a processor reads or writes, the processor first checks whether target data exists in the cache. If yes, the processor first points to the cache rather than other storages (such as a memory). The multi-level cache architecture improves the access performance. Upon an access to a Level 1 Cache, if no target data exists in the Level 1 Cache, that is, there is a miss, a Level 2 Cache will be accessed. If no target data exists in the Level 2 Cache either, a cache of a next level will be accessed, until the target data is acquired. Although the multi-level cache architecture sets the Level 1 Cache and Level 2 Cache to reduce an access delay and sets a Level 3 Cache to reduce a miss rate, the introduction of the multi-level cache architecture also increases a delay in accessing each level of cache. For example: it takes 6 cycles from a miss upon the access to the Level 1 Cache to the access to the Level 2 Cache, and it takes 8 cycles from a miss upon the access to the Level 2 Cache to the access to the Level 3 Cache.
As shown, although the multi-level cache architecture is set to reduce the access delay, in case of a miss upon a cache access and a low hit rate, the access delay caused by a level-by-level access to each level of cache will accumulate gradually, which finally results in a significant delay. Moreover, a level-by-level access to each level of cache will generate redundant power consumption. In case of simultaneously accessing each level of cache, although the hit rate for target data acquisition may be improved and the misses may be reduced, there will be more redundant power consumption.